In memory applications, a storage device may include a controller that sends a complementary pair of clock signals to a memory die in order to read data from the memory die. In response to the clock signals, the memory die may align data pulses of data signals to the edges of the clock signals and send the aligned data signals along with clocks signals back to the controller. The controller may then process the data signals using the clock signals.
Typically, the clocks signals have a 50% duty cycle. In an ideal situation, the controller generates the clock signals with the 50% duty cycle, and the duty cycle remains at 50% throughout the read process. That is, the memory die retrieving the data for the controller receives the clock signals with the 50% duty cycle, maintains the duty cycle at 50% while aligning the data, and transmits the clocks signals with a 50% duty cycle back to the controller.
However, in actual implementation, due to process-voltage-temperature (PVT) variations and silicon interface impact between the controller die and the memory die, the controller may not generate the clock signals with a 50% duty cycle and/or the duty cycle of clocks signals may shift away from the 50% duty cycle when the memory die aligns the data with the clock signals. Consequently, data valid window generated by these non-50% duty clock signals may shrink such that when the controller receives the data signals and the clock signals from the memory die, the controller may make errors in latching the data. For example, if the clock signals and the data signals are not properly aligned, the controller may miss sampling certain data pulses while sampling others twice. In addition or alternatively, if the duty cycle is sufficiently far from 50%, the controller's resistor-capacitor (RC) components may filter out or attenuate the edges of the clock signals. In turn, the controller may miss sampling certain data pulses because it failed to recognize a clock edge as occurring. In view of the errors that can result when the clock signals are generated away from 50% and/or when the duty cycle shifts away from 50% during data retrieval processes, duty cycle correction schemes that correct the duty cycle and move the duty cycle back to 50% are desirable for high speed data transfer.